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2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 1 of 49 product description the kxtf9 is a tri - axis +/ - 2g, +/ - 4g or +/ - 8g silicon micromachined accelerometer with integrated orientation, tap/double tap, and activity detecting algorithms. the sense element is fabricated using kionixs proprietary plasma micro machining process technology. acceleration sensing is based on the principle of a differential capacitance arising from acceleration - induced motion of the sense element, which further utilizes common mode cancellation to decrease errors from process variat ion, temperature, and environmental stress. the sense element is hermetically sealed at the wafer level by bonding a second silicon lid wafer to the device using a glass frit. a separate asic device packaged with the sense element provides signal condition ing, and intelligent user - programmable application algorithms. the accelerometer is delivered in a 3 x 3 x 0.9 mm lga plastic package operating from a 1.8 C 3.6v dc supply. i 2 c interface is used to communicate to the chip to configure and check updates to the orientation, directional tap tm detection and activity monitoring algorithms.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 2 of 49 functional diagram x sensor vdd io vdd gnd y sensor z sensor 10 i 2 c digital engine charge amp 5 1 4 a / d 9 7 digital filter
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 3 of 49 product specifications table 1. mechanical (specifications are for operation at 1.8v and t = 25c unless stated o therwise) parameters units min typical max operating temperature range o c - 40 - 85 zero - g offset mg - 125 - +125 zero - g offset variation from rt over temp. mg/ o c 0.7 (xy) 0.4 (z) sensitivity (12 - bit) 1 gsel1=0, gsel=0 ( 2g) counts/g 988 102 4 1060 gsel1=0, gsel0=1 ( 4g) 494 512 530 gsel1=1, gsel0=0 ( 8g) 247 256 265 sensitivity (8 - bit) 1 gsel1=0, gsel=0 ( 2g) counts/g 61 64 67 gsel1=0, gsel0=1 ( 4g) 30 32 34 gsel1=1, gsel0=0 ( 8g) 15 16 17 sensitivity variation from r t over temp. %/ o c 0.01 (xy) 0.03 (z) offset ratiometric error (v dd = 1.8 v 5 %) % 0.3 sensitivity ratiometric error (v dd = 1.8 v 5 %) % 0.4 (xy) 0.2 (z) self test output change on activation g 0.9 (x) 0.8 (y) 0.7 (z) mechanical resonance ( - 3db) 2 hz 3500 (xy) 1800 (z) non - linearity % of fs 1 cross axis sensitivity % 2 notes: 1. resolution and acceleration ranges are user selectable via i 2 c. 2. resonance as defined by the dampened mechanical sensor.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 4 of 49 t able 2. electrical (specifications are for operation at 1.8v and t = 25c unless stated otherwise) parameters units min typical max supply voltage (v dd ) operating v 1.8 1.8 3.6 i/o pads supply voltage (v io ) v 1.7 v dd current consumption all on (r es = 1) ? a 470 570 670 all on (res = 0) 230 standby 0.1 output low voltage 1 v - - 0.2 * v io output high voltage v 0.9 * v io - - input low voltage v - - 0.2 * v io input high voltage v 0.8 * v io - - input pull - down current ? a 0 start up time 2 res = 0 ms 0.050 res = 1, odr = 25 hz 80 res = 1, odr = 50hz 40 res = 1, odr = 100hz 20 res = 1, odr = 200hz 10 res = 1, odr = 400hz 5 res = 1, odr = 800hz 2.5 power up time 3 ms 20 i 2 c communica tion rate khz 400 output data rate (odr) 4 hz 25 50 800 bandwidth ( - 3db) 5 res = 0 khz 1.59 res = 1 hz odr/2 notes: 1. assuming i 2 c communication and minimum 1.5k ? pull - up resistor on scl and sda pins. assuming vio < 2v, if vio > 2 v then the maximum output low voltage is 0.4v. 2. start up time is from pc1 set to valid outputs. 3. power up time is from vdd valid to device boot completion. 4. user selectable through i 2 c. 5. user selectable and dependant on odr and res.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 5 of 49 table 3. environmental parameters units min typical max supply voltage (v dd ) absolute limits v - 0.3 - 6.0 operating temperature range o c - 40 - 85 storage temperature range o c - 55 - 150 mec h. shock (powered and unpowered) g - - 5000 for 0.5ms 10000 for 0.2ms esd hbm v - - 2000 caution: esd sensitive and mechanical shock sensitive component, improper handling can cause permanent damage to the device. this product conforms to directive 2002/95/ec of the european parliament and of the council of the european union (rohs). specifically, this product does not contain lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyls (pbb), or polybrominated diphenyl ethers (pbd e) above the maximum concentration values (mcv) by weight in any of its homogenous materials. homogenous materials are "of uniform composition throughout." this product is halogen - free per iec 61249 - 2 - 21. specifically, the materials used in this produc t contain a maximum total halogen content of 1500 ppm with less than 900 - ppm bromine and less than 900 - ppm chlorine. soldering soldering recommendations are available upon request or from www.kionix.com . hf
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 6 of 49 applicat ion schematic table 4. kxtf9 pin descriptions pin name description 1 io vdd the power supply input for the digital communication bus. decouple this pin to ground with a 0.1uf ceramic capacitor. 2 dnc reserved C do no t connect 3 dnc reserved C do not connect 4 gnd ground 5 vdd the power supply input. decouple this pin to ground with a 1uf ceramic capacitor. 6 dnc reserved C do not connect 7 int physical interrupt 8 dnc reserved C do not connect 9 scl i 2 c serial clock 10 sda i 2 c serial data 1 2 3 4 5 6 7 8 9 1 0 v d d c 1 s c l s d a k x t f 9 i n t i o v d d c 2
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 7 of 49 test specifications ! special characteristics : these characteristics have been identified as being critical to the customer. every part is tested to verify its conformance to specification prior to shipment. table 5 . test specifications parameter specification test conditions zero - g offset @ rt 0 +/ - 128 counts 25c, vdd = 1.8 v sensitivity @ rt 1024 +/ - 35.8 counts/g 25c, vdd = 1.8 v current consumption -- operating 470 <= idd <= 670 ua 25c, vdd = 1.8 v
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 8 of 49 p ackage dimensions and orientation 3 x 3 x 0.9 mm lga all dimensions and tolerances conform to asme y14.5m - 1994
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 9 of 49 orientation when device is accelerated in +x, +y or +z direction, the corresponding output will increase. static x/y/ z output response versus orientation to earths surface (1g): gsel1=0, gsel0=0 ( 2g) position 1 2 3 4 5 6 diagram top bottom bottom top resolution (bits) 12 8 12 8 12 8 12 8 12 8 12 8 x (counts) 0 0 1024 64 0 0 - 1024 - 64 0 0 0 0 y (counts) 1024 64 0 0 - 1024 - 64 0 0 0 0 0 0 z (counts) 0 0 0 0 0 0 0 0 0 1024 64 - 1024 - 64 x - polarity 0 + 0 - 0 0 y - polarity + 0 - 0 0 0 z - polarity 0 0 0 0 + - (1g) earths surface pin 1 +x +y +z
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 10 of 49 static x/y/z output response versus orientation to earths surface (1g): gsel1=0, gsel0=1 ( 4g) position 1 2 3 4 5 6 diagram top bottom bottom top resolution (bits) 12 8 12 8 12 8 12 8 12 8 12 8 x (coun ts) 0 0 512 32 0 0 - 512 - 32 0 0 0 0 y (counts) 512 32 0 0 - 512 - 32 0 0 0 0 0 0 z (counts) 0 0 0 0 0 0 0 0 0 512 32 - 512 - 32 x - polarity 0 + 0 - 0 0 y - polarity + 0 - 0 0 0 z - polarity 0 0 0 0 + - (1g) earths surface
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 11 of 49 static x/y/z output response versus orientation to earths surface (1g): gsel1=1, gsel0=0 ( 8g) position 1 2 3 4 5 6 diagram top bottom bottom top resolution (bits) 12 8 12 8 12 8 12 8 12 8 12 8 x (counts) 0 0 256 16 0 0 - 256 - 16 0 0 0 0 y (counts) 256 16 0 0 - 256 - 16 0 0 0 0 0 0 z (counts) 0 0 0 0 0 0 0 0 0 256 16 - 256 - 16 x - polarity 0 + 0 - 0 0 y - polarity + 0 - 0 0 0 z - polarity 0 0 0 0 + - (1g) earths surface
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 12 of 49 kxtf9 digital interface the kionix kxtf9 digital accelerometer has the ability to communicate on the i 2 c digital serial interface bus. this flexibility allows for easy system integration by eliminating analog - to - digita l converter requirements and by providing direct communication with system micro - controllers. the serial interface terms and descriptions as indicated in table 6 below will be observed throughout this document. term description transmitter the device that transmits data to the bus. receiver the device that receives data from the bus. master the device that initiates a transfer, generates clock signals, and terminates a transfer. slave the device addressed by the master. table 6. serial interface terminologies i 2 c serial interface as previously mentioned, the kxtf9 has the ability to communicate on an i 2 c bus. i 2 c is primarily used for synchronous serial communication between a master device and one or more slave devices. the master, typically a micro controller, provides the serial clock signal and addresses slave devices on the bus. the kxtf9 always operates as a slave device during standard master - slave i 2 c operation. i 2 c is a two - wire serial interface that contains a serial clock (scl) lin e and a serial data (sda) line. scl is a serial clock that is provided by the master, but can be held low by any slave device, putting the master into a wait condition. sda is a bi - directional line used to transmit and receive data to and from the interf ace. data is transmitted msb (most significant bit) first in 8 - bit per byte format, and the number of bytes transmitted per transfer is unlimited. the i 2 c bus is considered free when both lines are high. i 2 c operation transactions on the i 2 c bus be gin after the master transmits a start condition (s), which is defined as a high - to - low transition on the data line while the scl line is held high. the bus is considered busy after this condition. the next byte of data transmitted after the start condit ion contains the slave address (sad) in the seven msbs (most significant bits), and the lsb (least significant bit) tells whether the master will be receiving data 1 from the slave or transmitting data 0 to the slave. when a slave address is sent, eac h device on the bus compares the seven msbs with its internally stored address. if they match, the device considers itself addressed by the master. the slave address associated with the kxtf9 is 0001111.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 13 of 49 it is mandatory that receiving devices acknowledg e (ack) each transaction. therefore, the transmitter must release the sda line during this ack pulse. the receiver then pulls the data line low so that it remains stable low during the high period of the ack clock pulse. a receiver that has been address ed, whether it is master or slave, is obliged to generate an ack after each byte of data has been received. to conclude a transaction, the master must transmit a stop condition (p) by transitioning the sda line from low to high while scl is high. the i 2 c bus is now free. writing to a kxtf9 8 - bit register upon power up, the master must write to the kxtf9s control registers to set its operational mode. therefore, when writing to a control register on the i 2 c bus, as shown sequence 1 on the following pa ge, the following protocol must be observed: after a start condition, sad+w transmission, and the kxtf9 ack has been returned, an 8 - bit register address (ra) command is transmitted by the master. this command is telling the kxtf9 to which 8 - bit register the master will be writing the data. since this is i 2 c mode, the msb of the ra command should always be zero (0). the kxtf9 acknowledges the ra and the master transmits the data to be stored in the 8 - bit register. the kxtf9 acknowledges that it has rece ived the data and the master transmits a stop condition (p) to end the data transfer. the data sent to the kxtf9 is now stored in the appropriate register. the kxtf9 automatically increments the received ra commands and, therefore, multiple bytes of data can be written to sequential registers after each slave ack as shown in sequence 2 on the following page. reading from a kxtf9 8 - bit register when reading data from a kxtf9 8 - bit register on the i 2 c bus, as shown in sequence 3 on the next page, the foll owing protocol must be observed: the master first transmits a start condition (s) and the appropriate slave address (sad) with the lsb set at 0 to write. the kxtf9 acknowledges and the master transmits the 8 - bit ra of the register it wants to read. th e kxtf9 again acknowledges, and the master transmits a repeated start condition (sr). after the repeated start condition, the master addresses the kxtf9 with a 1 in the lsb (sad+r) to read from the previously selected register. the slave then acknowled ges and transmits the data from the requested register. the master does not acknowledge (nack) it received the transmitted data, but transmits a stop condition to end the data transfer. note that the kxtf9 automatically increments through its sequential registers, allowing data to be read from multiple registers following a single sad+r command as shown below in sequence 4 on the following page. if a receiver cannot transmit or receive another complete byte of data until it has performed some other fun ction, it can hold scl low to force the transmitter into a wait state. data transfer only continues when the receiver is ready for another byte and releases scl.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 14 of 49 data transfer sequences the following information clearly illustrates the variety of data transfers that can occur on the i 2 c bus and how the master and slave interact during these transfers. table 7 defines the i 2 c terms used during the data transfers. term definition s start condition sr repeated start condition sad slave address w write bit r read bit ack acknowledge nack not acknowledge ra register address data transmitted/received data p stop condition table 7. i 2 c terms sequence 1. the master is writing one byte to the slave. master s sad + w ra data p sl ave ack ack ack sequence 2. the master is writing multiple bytes to the slave. master s sad + w ra data data p slave ack ack ack ack sequence 3. the master is receiving one byte of data from the slave. master s sad + w ra sr sad + r nack p slave ack ack ack data sequence 4. the master is receiving multiple bytes of data from the slave. master s sad + w ra sr sad + r ack nack p slave ack ack ack data data
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 15 of 49 kxtf9 e mbedded registers the kxtf9 has 39 embedded 8 - bit registers that are accessible by the user. this section contains the addresses for all embedded registers and also describes bit functions of each register. table 8 below provides a listing of the access ible 8 - bit registers and their addresses. register name type i2c read/write address read/write hex binary xout_hpf_l r 0x00 0000 0000 xout_hpf_h r 0x01 0000 0001 yout_hpf_l r 0x02 0000 0010 yout_hpf_h r 0x03 0000 0011 zout_hp f_l r 0x04 0001 0100 zout_hpf_h r 0x05 0001 0101 xout_l r 0x06 0000 0110 xout_h r 0x07 0000 0111 yout_l r 0x08 0000 1000 yout_h r 0x09 0000 1001 zout_l r 0x0a 0001 1010 zout_h r 0x0b 0001 1011 dcst_resp r 0x0c 0000 1100 not used - 0x0d 0000 1101 not used - 0x0e 0000 1110 who_am_i r 0x0f 0000 1111 tilt_pos_cur r 0x10 0001 0000 tilt_pos_pre r 0x11 0001 0001 kionix reserved - 0x12 0001 0010 kionix reserved - 0x13 0001 0011 kionix reserved - 0x14 0001 0100 int_src_reg1 r 0x15 0001 0101 int_src _reg2 r 0x16 0001 0110 not used - 0x17 0001 0111 status_reg r 0x18 0001 1000 not used - 0x19 0001 1001 int_rel r 0x1a 0001 1010 ctrl_reg1* r/w 0x1b 0001 1011
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 16 of 49 ctrl_reg2* r/w 0x1c 0001 1100 ctrl_reg3* r/w 0x1d 0001 1101 int_ctrl_reg1* r/w 0x1e 0001 1 110 int_ctrl_reg2* r/w 0x1f 0001 1111 int_ctrl_reg3* r/w 0x20 0010 0000 data_ctrl_reg* r/w 0x21 0010 0001 not used - 0x22 C 0x27 - tilt_timer* r/w 0x28 0010 1000 wuf_timer* r/w 0x29 0010 1001 not used - 0x2a 0010 1010 tdt_timer* r/w 0x2b 0010 1011 tdt_h_thresh* r/w 0x2c 0010 1100 tdt_l_thresh* r/w 0x2d 0010 1101 tdt_tap_timer* r/w 0x2e 0010 1110 tdt_total_timer* r/w 0x2f 0010 1111 tdt_latency_timer* r/w 0x30 0011 0000 tdt_window_timer* r/w 0x31 0011 0001 reserved - 0x32 C 0x39 - self_test r/ w 0x3a 0011 1010 reserved - 0x3b C 0x59 - wuf_thresh* r/w 0x5a 0101 1010 reserved - 0x5b 0101 1011 tilt_angle* r/w 0x5c 0101 1100 reserved - 0x5d C 0x5e - hyst_set* r/w 0x5f 0101 1111 * note: when changing the contents of these registers, the pc1 bit in ctrl_reg1 must first be set to 0. table 8. kxtf9 register map
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 17 of 49 kxtf9 register descriptions accelerometer outputs these registers contain up to 12 - bits of valid acceleration data for each axis depending on the setting of the res bit in ctrl_ reg1, where the acceleration outputs are represented in 12 - bit valid data when res = 1 and 8 - bit valid data when res = 0. the data is updated every user - defined odr period, is protected from overwrite during each read, and can be converted from digita l counts to acceleration (g) per figure 9. the register acceleration output binary data is represented in 2s complement format. for example, if n = 12 bits, then the counts range is from - 2048 to 2047, and if n = 8 bits, then the counts range is from - 12 8 to 127. 12 - bit register data (2s complement) equivalent counts in decimal range = +/ - 2g range = +/ - 4g range = +/ - 8g 0111 1111 1111 2047 +1.999g +3.998g +7.996g 0111 1111 1110 2046 +1.998g +3.996g +7.992g 8 - bit register data (2s complement) equivalent cou nts in decimal range = +/ - 2g range = +/ - 4g range = +/ - 8g 0111 1111 127 +1.984g +3.968g +7.936g 0111 1110 126 +1.968g +3.936g +7.872g figure 9. acceleration (g) calculation
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 18 of 49 xout_hpf_l x - axis high - pass filtered accelerometer output least significant byte r r r r r r r r xoutd3 xoutd2 xoutd1 xo utd0 x x x x bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x00h xout_hpf_h x - axis high - pass filtered accelerometer output most significant byte r r r r r r r r xoutd11 xoutd10 xoutd9 xoutd8 xoutd7 xoutd6 xoutd5 xoutd4 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x01h yout_hpf_l y - axis high - pass filtered accelerometer output least significant byte r r r r r r r r youtd3 youtd2 youtd1 youtd0 x x x x bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c add ress: 0x02h yout_hpf_h y - axis high - pass filtered accelerometer output most significant byte r r r r r r r r youtd11 youtd10 youtd9 youtd8 youtd7 youtd6 youtd5 youtd4 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x03h
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 19 of 49 zout_hpf_l z - axis high - pass filtered accelerometer output least significant byte r r r r r r r r zoutd3 zoutd2 zoutd1 zoutd0 x x x x bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i2c address: 0x04h zout_hpf_h z - axis high - pass filtered accelero meter output most significant byte r r r r r r r r zoutd11 zoutd10 zoutd9 zoutd8 zoutd7 zoutd6 zoutd5 zoutd4 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x05h xout_l x - axis accelerometer output least significant byte r r r r r r r r xoutd3 xoutd2 xoutd1 xoutd0 x x x x bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x06h xout_h x - axis accelerometer output most significant byte r r r r r r r r xoutd11 xoutd10 xoutd9 xoutd8 xoutd7 xoutd6 xoutd5 xoutd4 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x07h
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 20 of 49 yout_l y - axis accelerometer output least significant byte r r r r r r r r youtd3 youtd2 youtd1 youtd0 x x x x bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x08h yout_h y - axis accelerometer output most significant byte r r r r r r r r youtd11 youtd10 youtd9 youtd8 youtd7 youtd6 youtd5 youtd4 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x09h zout_l z - axis accelerometer output least significant byte r r r r r r r r zoutd3 zoutd2 zoutd1 zoutd0 x x x x bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i2c address: 0x0ah zout_h z - axis accelerometer output most significant byte r r r r r r r r zoutd11 zoutd10 zoutd9 zoutd8 zoutd7 zoutd6 zoutd5 zoutd4 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x0bh
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 21 of 49 dcst_resp this register can be used to verify proper integrated circuit functionality. it always has a byte value of 0x55h unless the dcst bit in ct rl_reg3 is set. at that point this value is set to 0xaah. the byte value is returned to 0x55h after reading this register. r r r r r r r r dcstr7 dcstr6 dcstr5 dcstr4 dcstr3 dcstr2 dcstr1 dcstr0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 010 10101 i 2 c address: 0x0ch who_i_am this register can be used for supplier recognition, as it can be factory written to a known byte value. the default value is 0x 01 h. r r r r r r r r wia7 wia6 wia5 wia4 wia3 wia2 wia1 wia0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000001 i 2 c address: 0x0fh
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 22 of 49 tilt position registers these two registers report previous and current position data that is updated at the user - defined odr frequency and is protected during register read. table 9 describes the reported position for each bit value. tilt_pos_cur current tilt position register r r r r r r r r reset value 0 0 le ri do up fd fu 00100000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x10h tilt_pos_pre previous tilt position register r r r r r r r r reset value 0 0 le ri do up fd fu 00100000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x11h bit description le left state (x - ) ri right state (x+) do down s tate (y - ) up up state (y+) fd face - down state (z - ) fu face - up state (z+) table 9. kxtf9 tilt position
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 23 of 49 interrupt source registers these two registers report function state changes. this data is updated when a new state change or event occurs and ea ch applications result is latched until the interrupt release register is read. the motion interrupt bit wufs can be configured to report data in an unlatched manner via the interrupt control registers. int_src_reg1 this register reports which axis and direction detected a single or double tap event, per table 10. r r r r r r r r 0 0 tle tri tdo tup tfd tfu bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x15h bit description tle x negative (x - ) reported tri x positive (x+) reported tdo y negative (y - ) reported tup y positive (y+) reported tfd z negative (z - ) reported tfu z positive (z+) reported table 10. kxtf9 directional tap tm reporting int_src_reg2 this register reports which function caused an interrupt. readin g from the interrupt release register will clear the entire contents of this register. r r r r r r r r 0 0 0 drdy tdts1 tdts0 wufs tps bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x16h drdy indicates that new acceleration data i s available. this bit is cleared when acceleration data is read or the interrupt release register is read. drdy = 0 C new acceleration data not available drdy = 1 C new acceleration data available
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 24 of 49 tdts1, tdts0 indicates whether a single or double - tap event was detected per table 11. tdts1 tdts0 event 0 0 no tap 0 1 single tap 1 0 double tap 1 1 dne table 11. directional tap tm event description tps reflects the status of the tilt position function. tps = 0 C tilt position state has not changed tps = 1 C tilt position state has changed status_reg this register reports the status of the interrupt. r r r r r r r r 0 0 0 int 0 0 0 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x18h int reports the combined inter rupt information of all enabled functions. this bit is released to 0 when the interrupt source latch register (1ah) is read. int = 0 C no interrupt event int = 1 C interrupt event has occurred
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 25 of 49 int_rel latched interrupt source information (int_src_reg1 and int_src_reg2), the status register, and the physical interrupt pin (7) are cleared when reading this register. r r r r r r r r x x x x x x x x bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x1ah ctrl_reg1 read/write control register that controls the main feature set. r/w r/w r/w r/w r/w r/w r/w r/w reset value pc1 res drdye gsel1 gsel0 tdte wufe tpe 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x1bh pc1 controls the operating mode of th e kxtf9. pc1 = 0 - stand - by mode pc1 = 1 C operating mode res determines the performance mode of the kxtf9. note that to change the value of this bit, the pc1 bit must first be set to 0. res = 0 C low current, 8 - bit valid res = 1 - high current, 12 - bit valid drdye enables the reporting of the availability of new acceleration data on the interrupt. note that to change the value of this bit, the pc1 bit must first be set to 0. drdye = 0 C availability of new acceleration data not reflected on interrupt pin (7) drdye = 1 - availability of new acceleration data reflected on interrupt pin (7)
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 26 of 49 gsel1, gsel0 selects the acceleration range of the accelerometer outputs per table 12. note that to change the value of this bit, the pc1 bit must first b e set to 0. gsel1 gsel0 range 0 0 +/ - 2g 0 1 +/ - 4g 1 0 +/ - 8g 1 1 na table 12. selected acceleration range tdte enables the directional tap tm function that will detect single and double tap events. note that to change the value of this bit, the pc1 bit must first be set to 0. tdte = 0 C disable tdte = 1 - enable wufe enables the wake up (motion detect) function that will detect a general motion event. note that to change the value of this bit, the pc1 bit must first be set to 0. wufe = 0 C disable wufe = 1 - enable tpe enables the tilt position function that will detect changes in device orientation. note that to change the value of this bit, the pc1 bit must first be set to 0. tpe = 0 C disable tpe = 1 - enable
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 27 of 49 ctrl_reg2 read/writ e control register that controls tilt position state enabling. per table 13, if a states bit is set to one (1), a transition into the corresponding orientation state will generate an interrupt. if it is set to zero (0), a transition into the correspondi ng orientation state will not generate an interrupt. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value 0 0 lem rim dom upm fdm fum 00111111 bit7 bit 6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x1ch bit description lem left state rim right state dom down state upm up state fdm face - down state fum face - up state table 13. tilt position state enabling
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 28 of 49 ctrl_reg3 read/writ e control register that provides more feature set control. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value srst otpa otpb dcst otdta otdtb owufa ow ufb 01001101 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x1dh srst initiates software reset, which performs the ram reboot routine. this bit will remain 1 until the ram reboot routine is finished. srst = 0 C no action srst = 1 C start ram reboot routine otpa, otpb sets the output data rate for the tilt position function per table 14. the default tilt position odr is 12.5hz. otpa otpb output data rate 0 0 1.6hz 0 1 6.3hz 1 0 12.5hz 1 1 50hz table 14. tilt position fu nction output data rate dcst initiates the digital communication self - test function. dcst = 0 C no action dcst = 1 C sets st_resp register to 0xaah and when st_resp is read, sets this bit to 0 and sets st_resp to 0x55h
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 29 of 49 otdta, otdtb sets the output da ta rate for the directional tap tm function per table 15. the default directional tap tm odr is 400hz. otdta otdtb output data rate 0 0 50hz 0 1 100hz 1 0 200hz 1 1 400hz table 15. directional tap tm function output data rate owufa, owufb sets the o utput data rate for the general motion detection function and the high - pass filtered outputs per table 16. the default motion wake up odr is 50hz. owufa owufb output data rate 0 0 25hz 0 1 50hz 1 0 100hz 1 1 200hz table 16. motion wake up func tion output data rate
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 30 of 49 int_ctrl_reg1 this register controls the settings for the physical interrupt pin (7). note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w re set value 0 0 ien iea iel ieu 0 0 00010000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x1eh ien enables/disables the physical interrupt pin (7) ien = 0 C physical interrupt pin (7) is disabled ien = 1 C physical interrupt pin (7) is enabled iea sets the polarity of the physical interrupt pin (7) iea = 0 C polarity of the physical interrupt pin (7) is active low iea = 1 C polarity of the physical interrupt pin (7) is active high iel sets the response of the physical interrupt pin (7) iel = 0 C the physical interrupt pin (7) latches until it is cleared by reading int_rel iel = 1 C the physical interrupt pin (7) will transmit one pulse with a period of 0.05ms ieu sets an alternate unlatched response for the physi cal interrupt pin (7) when the motion interrupt feature (wuf) only is enabled. ieu = 0 C the physical interrupt pin (7) latches or pulses per the iel bit until it is cleared by reading int_rel ieu = 1 C the physical interrupt pin (7) will follow an unlat ched response if the motion interrupt feature is enabled
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 31 of 49 int_ctrl_reg2 this register controls motion detection axis enabling. per table 17, if an axis bit is set to one (1), a motion on that axis will generate an interrupt. if it is set to zero (0), a motion on that axis will not generate an interrupt. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value xbw ybw zbw 0 0 0 0 0 11100000 bit7 bit6 bi t5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x1fh bit description xbw x - axis motion ybw y - axis motion zbw z - axis motion table 17. motion detection axis enabling
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 32 of 49 int_ctrl_reg3 this register controls the tap detection direction ax is enabling. per table 18, if a directions bit is set to one (1), a single or double tap in that direction will generate an interrupt. if it is set to zero (0), a single or double tap in that direction will not generate an interrupt. note that to prop erly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value 0 0 tlem trim tdom tupm tfdm tfum 00111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x20h bit description tlem x negative (x - ) trim x positive (x+) tdom y negative (y - ) tupm y positive (y+) tfdm z negative (z - ) tfum z positive (z+) table 18. directional tap tm axis mask
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 33 of 49 data_ctrl_reg read/write control register that configu res the acceleration outputs. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value 0 0 hpfroa hprob 0 osaa osab osac 00000010 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x21h hpfroa, hpfrob sets the roll - off frequency for the first - order high - pass filter in conjunction with the output data rate (owufa, owufb) that is chosen for the hpf acceleration outputs that are used in th e motion wake up (wuf) application per table 19. note that this roll - off frequency is also applied to the x, y and z high - pass filtered outputs. high - pass filter configuration hpfroa hpfrob beta hpf roll - off (hz) 0 0 7/8 odr / 50 0 1 15/16 odr / 100 1 0 31/32 odr / 200 1 1 63/64 odr / 400 table 19. high - pass filter roll - off frequency osaa, osab, osac sets the output data rate (odr) for the low - pass filtered acceleration outputs per table 20. osaa osab osac output data rate lpf roll - off 0 0 1 25hz 12.5hz 0 1 0 50hz 25hz 0 1 1 100hz 50hz 1 0 0 200hz 100hz 1 0 1 400hz 200hz 1 1 0 800hz 400hz 1 1 1 does not exist does not exist table 20. lpf acceleration output data rate (odr)
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 34 of 49 tilt_timer this register is the initial count register for the tilt position state timer (0 to 255 counts). every count is calculated as 1/odr delay period, where the odr is user - defined per table 14. a new state must be valid as many measurement periods before the change is accepted. note that to properly cha nge the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value tsc7 tsc6 tsc5 tsc4 tsc3 tsc2 tsc1 tsc0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x28h wuf_timer this register is the initial count register for the motion detection timer (0 to 255 counts). every count is calculated as 1/odr delay period, where the odr is user - defined per table 16. a new state must be valid as many measurement periods b efore the change is accepted. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value wufc7 wufc6 wufc5 wufc4 wufc3 wufc2 wufc1 wufc0 00000000 bit7 bit6 bi t5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x29h tdt_timer this register contains counter information for the detection of a double tap event. every count is calculated as 1/odr delay period, where the odr is user - defined per table 15. t dt_timer represents the minimum time separation between the first tap and the second tap in a double tap event. the kionix recommended default value is 0.3 seconds (0x78h). note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value tdtc7 tdtc6 tdtc5 tdtc4 tdtc3 tdtc2 tdtc1 tdtc0 01111000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x2bh
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 35 of 49 tdt_h_thresh this register represents the 9 - bit jerk high threshold to determine if a tap is detected. the performance index (pi) is the jerk signal that is expected to be less than this threshold, but greater than the tdt_l_thresh threshold during single and double tap events. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. the kionix recommended default value is 182 (0xb6h) and the performance index is calculated as: x = x(current) C x(previous) y = y(current) C y(previous) z = z(curre nt) C z(previous) pi = |x| + |y| + |z| equation 1. performance index r/w r/w r/w r/w r/w r/w r/w r/w reset value tth8 tth7 tth6 tth5 tth4 tth3 tth2 tth1 10110110 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x2ch tdt_l_t hresh this register represents the 7 - bit jerk low threshold to determine if a tap is detected. the performance index (pi) is the jerk signal that is expected to be greater than this threshold and less than the tdt_h_thresh threshold during single and doub le tap events. this register also contains the lsb of the tdt_h_thresh threshold. the kionix recommended default value is 26 (0x1ah). note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value tth0 ttl6 ttl5 ttl4 ttl3 ttl2 ttl1 ttl0 00011010 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x2dh
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 36 of 49 tdt_tap_timer this register contains counter information for the detection of any tap event . every count is calculated as 1/odr delay period, where the odr is user - defined per table 17. in order to ensure that only tap events are detected, these time limits are used. a tap event must be above the performance index threshold (tdt_thresh) for a t least the low limit (ftdl0 C ftdl2) and no more than the high limit (ftdh0 C ftdh4). the kionix recommended default value for the high limit is 0.05 seconds and for the low limit is 0.005 seconds (0xa2h). note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value ftdh4 ftdh3 ftdh2 ftdh1 ftdh0 ftdl2 ftdl1 ftdl0 10100010 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x2eh tdt_total_t imer this register contains counter information for the detection of a double tap event. every count is calculated as 1/odr delay period, where the odr is user - defined per table 17. in order to ensure that only tap events are detected, this time limit is used. this register sets the total amount of time that the two taps in a double tap event can be above the pi threshold (tdt_l_thresh). the kionix recommended default value for tdt_total_timer is 0.09 seconds (0x24h). note that to properly change the v alue of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value std7 std6 std5 std4 std3 std2 std1 std0 00100100 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x2fh
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 37 of 49 tdt_ latency_timer this register contains counter information for the detection of a tap event. every count is calculated as 1/odr delay period, where the odr is user - defined per table 17. in order to ensure that only tap events are detected, this time limit is used. this register sets the total amount of time that the tap algorithm will count samples that are above the pi threshold (tdt_l_thresh) during a potential tap event. it is used during both single and double tap events. however, reporting of single taps on the physical interrupt pin (7) will occur at the end of the tdt_window_timer. the kionix recommended default value for tdt_latency_timer is 0.1 seconds (0x28h). note that to properly change the value of this register, the pc1 bit in ctrl_reg1 mu st first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value tlt7 tlt6 tlt5 tlt4 tlt3 tlt2 tlt1 tlt0 00101000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x30h tdt_window_timer this register contains counter informa tion for the detection of single and double taps. every count is calculated as 1/odr delay period, where the odr is user - defined per table 17. it defines the time window for the entire tap event, single or double, to occur. reporting of single taps on t he physical interrupt pin (7) will occur at the end of this tap window. the kionix recommended default value for tdt_window_timer is 0.4 seconds (0xa0h). note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value tws7 tws6 tws5 tws4 tws3 tws2 tws1 tws0 10100000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x31h self_test when 0xca is written to this register, the mems self - test func tion is enabled. electrostatic - actuation of the accelerometer, results in a dc shift of the x, y and z axis outputs. writing 0x00 to this register will return the accelerometer to normal operation. r/w r/w r/w r/w r/w r/w r/w r/w reset value 1 1 0 0 1 0 1 0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x3ah
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 38 of 49 wuf_thresh this register sets the acceleration threshold, wuf threshold that is used to detect a general motion input. the kxtf9 will ship from the factory wit h wuf_thresh set to a change in acceleration of 0.5g. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value wufth7 wufth6 wufth5 wufth4 wufth3 wufth2 wu fth1 wufth0 00001000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x5ah tilt_angle this register sets the tilt angle that is used to detect the transition from face - up/face - down states to screen rotation states. the kxtf9 ships from the factory with tilt angle set to a low threshold of 26 from horizontal. a different default tilt angle can be requested from the factory. note that the minimum suggested tilt angle is 10. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value ta7 ta6 ta5 ta4 ta3 ta2 ta1 ta0 00001100 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x5ch hyst_set this register sets the hystere sis that is placed in between the screen rotation states. the kxtf9 ships from the factory with hyst_set set to +/ - 15 of hysteresis. a different default hysteresis can be requested from the factory. note that when writing a new value to this register t he current values of res0, res1, res2 and res3 must be preserved. these values are set at the factory and must not change. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value res2 res1 res0 hyst4 hyst3 hyst2 hyst1 hyst0 --- 10100 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x5fh
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 39 of 49 kxtf9 embedded applications orientation detection feature the orientation detection feature of the kxtf9 will report changes in face up, face down, +/ - vertical and +/ - horizontal orientation. this intelligent embedded algorithm considers very important factors that provide accurate orientation detection from low cost tri - axis accelerometers. fac tors such as: hysteresis, device orientation angle and delay time are described below as these techniques are utilized inside the kxtf9. hysteresis a 45 tilt angle threshold seems like a good choice because it is halfway between 0 and 90. however, a problem arises when the user holds the device near 45. slight vibrations, noise and inherent sensor error will cause the acceleration to go above and below the threshold rapidly and randomly, so the screen will quickly flip back and forth between the 0 and the 90 orientations. this problem is avoided in the kxtf9 by choosing a 30 threshold angle. with a 30 threshold, the screen will not rotate from 0 to 90 until the device is tilted to 60 (30 from 90). to rotate back to 0, the user must tilt back to 30, thus avoiding the screen flipping problem. this example essentially applies +/ - 15 of hysteresis in between the four screen rotation states. table 21 shows the acceleration limits implemented for 30. orientation x acceleration (g) y acce leration (g) 0/360 - 0.5 < a x < 0.5 a y > 0.866 90 a x > 0.866 - 0.5 < a y < 0.5 180 - 0.5 < a x < 0.5 a y < - 0.866 270 a x < - 0.866 - 0.5 < a y < 0.5 table 21. acceleration at the four orientations with +/ - 15 of hysteresis
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 40 of 49 the kxtf9 allows the user to change the amount of hysteresis in between the four screen rotation states. by simply writing to the hyst_set register, the user can adjust the amount of hysteresis up to +/ - 45. the plot in figure 1 shows the typical amount of hysteresis applied for a given digital count value of hyst_set. figure 1. hyst_set vs hysteresis hyst_set vs hysteresis 0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 hyst_set value (counts) hysteresis (+/- degrees) hysteresis
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 41 of 49 device orientation angle (aka tilt angle) to ensure that horizontal and vertical device orientation changes are detected, even when it isnt in the ideal vertical orientation C where the angle in figure 2 is 90, the kxtf9 considers device orientation angle in its algorithm. figure 2. device orientation angle as the angle in figure 2 is decreased, the maximum gravitational acceleration on the x - axis or y - axis will also de crease. therefore, when the angle becomes small enough, the user will not be able to make the screen orientation change. when the device orientation angle approaches 0 (device is flat on a desk or table), ax = ay = 0g, az = +1g, and there is no way to d etermine which way the screen should be oriented, the internal algorithm determines that the device is in either the face - up or face - down orientation, depending on the sign of the z - axis. the kxtf9 will only change the screen orientation when the orientat ion angle is above the factory - defaulted/user - defined threshold set in the tilt_angle register. equation 2 can be used to determine what value to write to the tilt_angle register to set the device orientation angle. tilt_angle (counts) = sin * (32 ( counts/g)) equation 2. tilt angle threshold tilt timer the 8 - bit register, tilt_timer can be used to qualify changes in orientation. the kxtf9 does this by incrementing a counter with a size that is specified by the value in tilt_timer for each set o f acceleration samples to verify that a change to a new orientation state is maintained. a user defined output data rate (odr) determines the time period for each sample. equation 3 shows how to calculate the tilt_timer register value for a desired delay time. tilt_timer (counts) = delay time (sec) x odr (hz) equation 3. tilt position delay time angle ?
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 42 of 49 motion interrupt feature description the motion interrupt feature of the kxtf9 reports qualified high - pass filtered acceleration based on the wake up (wuf) t hreshold. if the high - pass filtered acceleration on any axis is greater than the user - defined wake up threshold (wuf_thresh), the device has transitioned from an inactive state to an active state. when configured in the unlatched mode, the kxtf9 will rep ort when the motion event finished and the device has returned to an inactive state. equation 4 shows how to calculate the wuf_thresh register value for a desired wake up threshold. wuf_thresh (counts) = wake up threshold (g) x 16 (counts/g) equation 4. wake up threshold a wuf (wuf_timer) 8 - bit raw unsigned value represents a counter that permits the user to qualify each active/inactive state change. note that each wuf timer count qualifies 1 (one) user - defined odr period (owuf). equation 5 shows how to calculate the wuf_timer register value for a desired wake up delay time. wuf_timer (counts) = wake up delay time (sec) x owuf (hz) equation 5. wake up delay time
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 43 of 49 figure 3 below shows the latched response of the motion detection algorithm with wuf timer = 10 counts. figure 3. latched motion interrupt response 0g typical motion interrupt example hpf acceleration wuf threshold ex: delay counter = 10 motion 10 inactive wuf timer time
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 44 of 49 figure 4 below shows the unlatched response of the motion detection algorithm with wuf timer = 10 counts. figure 4. unlatched motion interrupt response 0g typical motion interrupt example hpf acceleration wuf threshold ex: delay counter = 10 motion 10 inactive wuf timer time
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 45 of 49 directional tap detection feature description the directional tap detection feature of the kxtf9 recognizes single and double tap inputs and reports the acceleration axis and direction that each tap occurred. eigh t performance parameters, as well as a user - selectable odr are used to configure the kxtf9 for a desired tap detection response. performance index the directional tap tm detection algorithm uses low and high thresholds to help determine when a tap ev ent has occurred. a tap event is detected when the previously described jerk summation exceeds the low threshold (tdt_l_thresh) for more than the tap detection low limit, but less than the tap detection high limit as contained in tdt_tap_timer. samples t hat exceed the high limit (tdt_h_thresh) will be ignored. figure 5 shows an example of a single tap event meeting the performance index criteria.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 46 of 49 figure 5. jerk summation vs threshold tdt_l_thresh : sampled data 3.14 3.15 3.16 3.17 3.18 3.19 3.2 3.21 0 20 40 60 80 100 120 140 160 180 calculated performance index time(sec) jerk (counts) pi
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 47 of 49 single tap detection the latency timer (tdt_latency_timer) set s the time period that a tap event will only be characterized as a single tap. a second tap has to occur outside of the latency timer. if a second tap occurs inside the latency time, it will be ignored as it occurred too quickly. the single tap will be reported at the end of the tdt_window_timer. figure 6 shows a single tap event meeting the pi, latency and window requirements. figure 6. single directional tap tm timing t dt_window_timer tdt_latency_timer tdt_l_thresh 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 0 20 40 60 80 100 120 140 160 calculated performance index time(sec) jerk (counts) pi
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 48 of 49 double tap detection an event can be characterized as a double tap only if the second tap crosses the performance index (tdt_l_thresh) outside the tdt_timer. this means that the tdt_timer determines the minimum time separation that must exist between the two taps of a double tap event. similar to the single tap, the second tap event must exceed the performance index for the time limit contained in tdt_tap_timer. the double tap will be reported at the end of the second tdt_latency_timer. figure 7 shows a double tap event meeting the pi, latency and window requirements. fig ure 7. double directional tap tm timing tdt_window_timer tdt_timer tdt_latency_timer tdt_latency_timer tdt_l_thresh 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 0 50 100 150 200 calculated performance index time(sec) jerk (counts) pi
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtf9 - 4100 rev. 6 jun - 2011 36 thornwood dr. C ithaca, ny 14850 ? 2010 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 425 - 2397 - 1106241613 www.kionix.com - info@kionix.com page 49 of 49 revision history revision description date 1 initial release 18 - dec - 2009 2 corrected default register values and table 15 references. 16 - mar - 2010 3 removed all references to 12.5 hz odr related to acceleration o utput registers and changed axes labels in figures 3 and 4. 01 - jul - 2010 4 updated drawing and photo with pin 1 marking 11 - oct - 2010 5 updated paragraph to include explanation of accelerometer output format in page 17 and updated figure 9 for 2's complemen t representation. updated static x/y/z output response versus orientation. 29 - mar - 2011 6 modified output low voltage level from 0.3vio to 0.2vio. also modified note1: assuming vio < 2v, if vio > 2 v then the maximum output low voltage is 0.4v. 24 - jun - 2011 "kionix" is a registered trademark of kionix, inc. products described herein are protected by patents issued or pending. no license is granted by implication or otherwise under any patent or other rights of kionix. the inf ormation contained herein is believed to be accurate and reliable but is not guaranteed. kionix does not assume responsibility for its use or distribution. kionix also reserves the right to change product specifications or discontinue t his product at an y time without prior notice. this publication supersedes and replaces all information previously supplied.

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